Quartus II (v10.0) + Cyclone II : JTAG Issues

I got the jtag chain working today by drilling a via and adding a wire to bypass the Vitesse PHY chip, leaving just the FPGA and CPLD in the chain. I still don't have a good answer as to why this worked, signal integrity looks comparable, but I can program my devices now.

As an interesting side note, originally I could properly scan the chain with an EthernetBlaster using the autodetect, but could not program, but the Rev C USB blaster gave me the same error that you describe above. After modding the board and bypassing the PHY, both the EthernetBlaster and USB blaster can scan the chain and program devices w/o issue. We could also properly boundary scan the board using Gopel's cascon software, but Quartus didn't want to play (Cascon runs the jtag chain at a much slower frequency however).

After confirming signal integrity looked good, I guessed that the PHY chip was the problem b/c we've done ~5 boards this year using FPGAs and CPLDs and haven't had any jtag issues, and this PHY is a 1st for us.