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Altera_Forum
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15 years ago

Quartus II (v10.0) + Cyclone II : JTAG Issues

Dear all, I have a JTAG chain of two devices. The first is a TI processor and the second a Cyclone II FPGA. Using the TI JTAG emulator and configuring it to 'bypass' the cyclone II with ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Your summary is correct and in the third schematic image you can scroll the jpg :) The 0 ohm on the TDO of the C2 is there in case the C2 is not loaded (it is a high cost option), so that allows for the TDO to be passed in the event the device is not there. To answer your question, TDO out of C2 pin 10 goes out to pin 7 of CN1.

TMS and TCK have the appropriate pull ups at the C2 device (shared line). TDI has the 1k pull up @ C2 but TI never had a requirement for it so it never got added to the front of the chain. I tried adding this yesterday with no luck. Same symptoms.

nCE? What Chip enable line are you referring to?