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Altera_Forum
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15 years ago

Quartus II (v10.0) + Cyclone II : JTAG Issues

Dear all, I have a JTAG chain of two devices. The first is a TI processor and the second a Cyclone II FPGA. Using the TI JTAG emulator and configuring it to 'bypass' the cyclone II with ...
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Altera_Forum
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15 years ago

let me summarize

jtag tdi comes from cn1a pin 3 goes to ti pin m9

from ti pin k9 as tdo to tdi fppga c2 pin 13 with 1k pull up to 3,3v

from fpga c2 tdo pin 10 to ??? with a 0R to ???

( i can't scroll your altium screenshot ;) )

from the datasheet and app notes for cyclone II configuration c2 page 55 figure 13-22 (http://www.altera.com/literature/hb/cyc2/cyc2_cii51013.pdf)

JTAG TMS & TDI need 1K pull up to 3,3V and TCK 1K pull down to GND

i have done some designs with 1k pull up at TMS and TDI but the datasheet has been changed a while ago

further more you must enshure that nCE is directly connected to GND do not use any resitance here in between