Quartus II Unexpected Simulation Of Clock Outputs

I have recently had to pick up an old Quartus II V5 project (schematics) from 2005 but have not done any logic design since then. Not wishing to encounter too steep a learning curve, I have installed Quartus II V9.1 SP2 Web Edition principally because I wanted to continue with the Altera simulator.

I have made the changes to the designs and been going through the verification process of simulation using some of the original project .vwf files. Everything was going well until I noticed some strange behaviour on a couple of outputs.

The device is a MAXII EPM2210 and the design includes a totally stand alone dual clock generator function which runs from a 7.5MHz input pin. This Clock input is fed directly to one output pin and via an inverter to another pin. External to the device, these two output signals are then routed back into the two Global Clock input pins.

What I have found recently is that the two clock output signals are not always coming out as 7.5Mhz during simulation. The output waveforms are not consistent in frequency but are always the invertion of each other.

I have reduced the simulation to include just these five signals and found that by simply changing the start position of the master input clock signal, the shape of the two clock outputs will be affected and eventually be square at 7.5MHz. Also, if I remove the two global clock inputs from the simulation, the outputs are good.

I have tried both Timing and Functional simulation and tried forcing LCELL use to extend delays which have not cleared the problem.

So Quartus seems adamant that there is a problem but I cannot help but feel this is a quirk somewhere in the IDE.

There are no warnings anywhere relating to this part of the project design.

Anybody seen this kind of thing before or got any ideas as to what could be causing this?

Thanks.