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Altera_Forum's avatar
Altera_Forum
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14 years ago

quartus II timing analyzer ignoring neg edge clk?

Tool is complaining about path from falling edge clock to rising edge, 25mhz, MAXII cpld. i would rather not ignore warning, how do i help timing analyzer understand, or me understand why it isn't h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

thanks again for reply,

I do think it was a false path, clk_819000_countNEG bus is from falling edge clk_cpld, and clk_819000_countNEG is feeding logic using ultimately captured on derived clk that is rising edge clk_cpld based.

thanks

process (clk_cpld)

begin

if (falling_edge (clk_cpld)) then

clk_8192000_countNEG <= clk_8192000_count;

end if;

end process;