quartus II timing analyzer ignoring neg edge clk?

Letting the tool fix is a good option, at least in this case.

As long as you have realistic timing constraints and they are met, it's fine.

However, there warning you were getting were not false paths and they were important. Ie, your circuit would not have worked correctly.

This is what you have

a) clk_8192000_countNEG is launched on the rising edge of clk_cpld.

b) there's some combinatory logic for the comparators

c) the result of b) is latched on the falling edge of clk_2048

However, both the rising edge and falling edge of clk_2048 are aligned with clk_cpld! But, because it's generate by logic, there's a relatively large skew between the clocks.

This is causing that at c), the hold time is being violated. And thus, the design would not behave correctly.