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Altera_Forum's avatar
Altera_Forum
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14 years ago

quartus II timing analyzer ignoring neg edge clk?

Tool is complaining about path from falling edge clock to rising edge, 25mhz, MAXII cpld. i would rather not ignore warning, how do i help timing analyzer understand, or me understand why it isn't h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you for taking the time to reply.

I understand your comments. The real system clock is 8.192Mhz, i just told the timing analyzer 25mhz for extra margin. I am currently using classic timing analyzer, but can see the need to move to timeQuest. After posting the question, if found the default setting under classic timing Analyzer does is not set to fix hold time for all paths. Once I changed it to all paths, all the warnings went away.

So even though i think the paths were false, i don't see any harm in letting tool fix them as it sees fit, a couple of ns change in the data or clock to i_dac_csn destination register won't matter since it has a half clock cycle.

Do you agree?