quartus II timing analyzer ignoring neg edge clk?

Hi,

1. I don't think your divider is producing a 2.048 MHz. In fact, since 25 isn't a multiple of 2.048 you can't divide a 25 MHz into exactly 2.048 MHz. You can divide it by 12 to get a 2.083 MHz clock though.

2. You need to use a "create_generated_clock" command to tell TimeQuest about clk_2048.

create_generated_clock -source clk -name clk_2048 -divide_by X [get_nets clk_2048]

The "get_nets" part may need some changes..

3. Using clock dividers often creates problems with skew and hold times. Most likely, even after adding the generated clock statement, you'll still have the problem.

Best solution is to replace the clk_2048 clock with a clock enable.

process (clk, reset)

if reset = '1' then

elsif clk'event and clk = '1' then

if enable = '1' then

-- Logic goes here

end if;

end if;

end process