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Altera_Forum
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14 years ago

Quartus II time limited .sof file

Hi, when I try to program my FPGA...it appears a advice window about a limited time .sof file generation...as shown in attached image. I'd like to know how I have to behave... Regards
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Altera_Forum
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8 years ago

Hi, I have a Query.

I'm using the EMAC IP from ALTERA. I only have tool licenses, But I don't have EMAC IP license. Can I add EMAC IP interface signals ( TXD and RXD) to signal tap logic analyzer?