Quartus-II synthesis/compile errors for Arria V device

I have been using Altera devices (Stratix, Cyclone and others) for more than 20 years. Recently our company decide to use the new Altera Arria V device. Our project has a lot math calculations of signed integers. The combinatory path can be very long. Typically from a registered value we need to do two 12-bit multiplys and 2 to 4 24-bit summation/substractions before the result is latched in the next stage flip-flop. The circuit runs with a low speed at 25MHz.

After some initial learning curve, we finally ran our design in the lab. But it did not work as we expected although we tried the same RTL code in FPGAs of another vendor. I then used SignalTap to view the key signals and found something wrong in one signal (at least). By tracing it further, I found for all the inputs the design should not cause the output overflow. However the captured result did show overflow.

In order for me to see more intermediate combinatory signals between the inputs to the result of that long path, I added a few debug registers, which inputs are connected to the signals I was interested without changing the original design. And then connect the output of these registers to CPU interface block so that they would not be optimized away. After doing that I have signals available for me to add to the SignalTap. To my surprise, the new compile did the calculation correctly in this path. No more overflow was observed. Then another bug showed up from other parts. I thought how could I trust the compile and then stopped trying in the lab.

Then I added a setting to export a gate-level netlist for my simulator. And I run the gate-level simulation of the chip (without timing back annotation). The second day when the simulation completes, I looked in the waveforms and verified that the error is duplicated in the simulation. It does appear that Quartus-II does not do as it should. Then I extracted the small part of the chip (3 modules) into a size-reduced "chip". After this small test chip is compiled, the gate-level simulation also showed the error. I then created a test bench to run both RTL and gate-level "chips" with the same inputs. I compare the outputs and printed error if they differ. For sure I got a lot error messages.

Has anyone else experienced the same issue with Arria V device comples? Has Altera come to you for the issue?

Thanks.