CLa_R
Occasional Contributor
5 years agoQuartus II stuck on 47% analisys
Hi,
my Quartus II 17.0 is stuck for hours (more than 8 hours) on 47% analisys. I am compiling for Cyclone IV E (ep4ce10...).
I noticed that, in my design (a simplified MISP CPU, mono clock), if I wired the final MUX selection signal with control signal, the compile is stuck on 47%.
If I fix the select signal of final MUX to a value (eg. VCC), my design compile in few seconds. But...why?
I am trying my design also with quartus 19.1 and the problem is the same.