Quartus ii stuck at Analysis and Synthesis

Thank you for your help.

I do pick different architectures on the upper level for the corresponding memory, where I do the port mapping.

The original version of my project is to input the data to each m_1 to m_50 in the testbench first, then do the sorting operation. It works fine but take long time to simulate. Thus I decide to cancel the inputting data process but add an mif file to each memory. Then I am experiencing this issue.

Here is how I pick the corresponding architecture and the port mapping:

entity processor is
port(......);
end entity;
architecture proc_rt0 of processor is
component control_unit is
   port( 
      ...
         ports for this component
      ...
   );
end component control_unit;
component mem is
   port(
      clock       : in std_logic := '0';
      data        : in std_logic_vector (31 downto 0);
      rdaddress   : in std_logic_vector (6 downto 0);
      wraddress   : in std_logic_vector (6 downto 0);
      wren        : in std_logic := '0';
      q           : out std_logic_vector(31 downto 0)
   );
end component mem;
signal m1_data : std_logic_vector(31 downto 0);
signal m1_rdad : std_logic_vector(6 downto 0);
signal m1_wrad : std_logic_vector(6 downto 0);
signal m1_wren : std_logic := '0';
signal m1_q    : std_logic_vector(31 downto 0);
for m_1: mem use entity work.mem(SYN0);--------------------------------pick corresponding architecture
begin
m_1 : mem port map(
   clock     => node_clock,
   data      => m1_data,
   rdaddress => m1_rdad,
   wraddress => m1_wrad,
   wren      => m1_wren,
   q         => m1_q
);
node_control_unit : control_unit port map (
   ......
   -- other ports mapping
   ......
   -- port connect to m_1
   cu_m1_data => m1_data,
   cu_m1_rdad => m1_rdad,
   cu_m1_wrad => m1_wrad,
   cu_m1_wren => m1_wren,
   cu_m1_q    => m1_q
);
end architecture proc_rt0;
architecture proc_rt1 of processor is
component control_unit is
   port( 
      ...
         ports for this component
      ...
   );
end component control_unit;
component mem is
   port(
      clock       : in std_logic := '0';
      data        : in std_logic_vector (31 downto 0);
      rdaddress   : in std_logic_vector (6 downto 0);
      wraddress   : in std_logic_vector (6 downto 0);
      wren        : in std_logic := '0';
      q           : out std_logic_vector(31 downto 0)
   );
end component mem;
signal m1_data : std_logic_vector(31 downto 0);
signal m1_rdad : std_logic_vector(6 downto 0);
signal m1_wrad : std_logic_vector(6 downto 0);
signal m1_wren : std_logic := '0';
signal m1_q    : std_logic_vector(31 downto 0);
for m_1: mem use entity work.mem(SYN1);--------------------------------pick corresponding architecture
begin
m_1 : mem port map(
   clock     => node_clock,
   data      => m1_data,
   rdaddress => m1_rdad,
   wraddress => m1_wrad,
   wren      => m1_wren,
   q         => m1_q
);
node_control_unit : control_unit port map (
   ......
   -- other ports mapping
   ......
   -- port connect to m_1
   cu_m1_data => m1_data,
   cu_m1_rdad => m1_rdad,
   cu_m1_wrad => m1_wrad,
   cu_m1_wren => m1_wren,
   cu_m1_q    => m1_q
);
end architecture proc_rt1;

Then I use the similar way to pick the corresponding architecture for the processor in the upper entity.

After I do some research online, I found the following page on altera website to do the initialization ram with multiple mif file which is the case I need to do. But it use verilog HDL, I am wondering if there is any way I can do it in the same way with vhdl?

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd11172006_639.html (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd11172006_639.html)

Thanks again for your help!