Forum Discussion
Altera_Forum
Honored Contributor
10 years agoHi,
I never tried, but the "examine" feature of the Quartus programmer should be able to do that: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08192010_758.html (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08192010_758.html). There also seems to be another thread about this topic: http://www.alteraforum.com/forum/showthread.php?t=42587 (http://www.alteraforum.com/forum/showthread.php?t=42587) However, this will of course only give you back the data stream, no source files (VHDL/Verilog). Best regards, GooGooCluster