Quartus II negative bus dimensions in Schematic file

you dont need schematics at all.

Just create a top level VHDL file that instatiates the sub-blocks and has a port declaration that would connect to pins on the device, and then go to Assignments -> Assignments editor and assign each of the top level IO's in the VHDL file to a pin. The top level IOs normally have to be std_logic or std_logic_vector.

As for simulation: what you normally do is create a VHDL Testbench, that controls all the IO to the block and clock generation. The testbench doesnt need to be synthesisable, so to generate a clock you can do something like:

  signal clk : std_logic := '0';
  signal reset : std_logic;
begin 
  reset <= '1', '0' after 50 ns;
  clk <= not clk after 10 ns;

and do all stimulus from the testbench. Normally you'd run something like this in modelsim.