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Altera_Forum
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12 years ago

Quartus II Linux 64bit 12.1/177 Archive Project questions

Howdy :-) We are working on a project that integrates VHDL logic from multiple design teams into an fpga. We typically get a new drop of VHDL from one of the teams, integrate it into the Quart...
Altera_Forum's avatar
Altera_Forum
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12 years ago

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Is there a way to avoid this difference?

By the way, I am using 13.1.

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I'm not sure. This is a good question to ask Altera directly. File a service request with Altera.

Create a simple project that you can use to demonstrate that the design changes for each synthesis run, and ask how to keep things from changing. Make sure your design is fully constrained (via a TimeQuest .sdc file).

Cheers,

Dave