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Altera_Forum
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12 years ago

Quartus II Linux 64bit 12.1/177 Archive Project questions

Howdy :-) We are working on a project that integrates VHDL logic from multiple design teams into an fpga. We typically get a new drop of VHDL from one of the teams, integrate it into the Quart...
Altera_Forum's avatar
Altera_Forum
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12 years ago

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It should not be indeterminate, i.e., resynthesizing with exactly the same starting seed should yield the same results. However,

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If using postFit, the result will be different. I guess the starting point is a little bit different after each compiling.

Is there a way to avoid this difference?

By the way, I am using 13.1.

-Tony