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Altera_Forum
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12 years ago

Quartus II Linux 64bit 12.1/177 Archive Project questions

Howdy :-) We are working on a project that integrates VHDL logic from multiple design teams into an fpga. We typically get a new drop of VHDL from one of the teams, integrate it into the Quart...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thanks Dave :-)

Thanks for the pointers!!

I just took the Quartus II Timing Designer classes, and learned that the output of the timing & fitting process is somewhat indeterminate. I'm not sure that is a problem, but I want to know which of the output files I need to save in order to remove that indeterminacy.