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Altera_Forum
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18 years ago

Quartus II Cyclone III DDR Memory problem

I am trying to use 32 MB DDR SDRAM in Cyclone III EP3C25F324C8. But when i compile the project, it gives me error saying The DQ group with DQS pin "mem_dqs_to_and_from_the_memddr[0]" has invali...
Altera_Forum's avatar
Altera_Forum
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17 years ago

It seems that not all DDR memory are assigned to the correct IO standard. Some seem to use default 2.5V standard. This should not happen with ddr_sdram_pin_assignments.tcl, but I can't see from the error message which signals are conflicting.

The difference between SSTL-x Class I and Class II doesn't matter in this respect, although it may important for correct operation of the design. You should expect that the design compiler selects the correct settings based on your hardware description.