Quartus II Cyclone III DDR Memory problem

I also have run into the same problem:

Error: altmemphy pin placement was unsuccessful
	Error: The DQ group with DQS pin "mem_dqs_to_and_from_the_ddr_sdram" has invalid DQ group assignments
		Error: The "2.5 V" I/O standard and/or the "Default" current strength on the pin "mem_dm_from_the_ddr_sdram" is not supported for DDR/DDR2 external memory interfaces

I'm trying to compile the standard design from the Altera Nios II Embedded Evaluation Kit, Cyclone III edition. I ran SOPC Builder, generated the design, came back to Quartus II and set the "cycloneIII_embedded_evaluation_kit_standard_sopc.v" file as the top-level file (rather than the default "cycloneIII_embedded_evaluation_kit_standard.v" which doesn't have the SOPC-based design in it). Then, as specified in the ddr and ddr2 sdram high-performance controller user guide (and echoed here in this thread), I ran the constraints file (ddr_sdram_pin_assignments.tcl) before I compiled the project. The Analysis & Synthesis phase completes Ok, but compilation fails during the Fitter phase.

Thus, I still see the error message listed above. I've checked the Assignment Editor, and all of the memory signals (such as mem_dq, mem_dqs, and mem_dm) are assigned to I/O Standard SSTL-2 Class I.

I'm not an expert with DDR SDRAM, so this message mystifies me. Should I change the I/O Standard to SSTL-2 Class II? Or is there some additional step I've overlooked?