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Altera_Forum
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12 years ago

Quartus II clock gating methodology

Hi All i'm using my FPGA (Stratix IV GX dev kit4) for ASIC prototyping. we use clock gating all around or design and when i'm using quartus i get poor QOR due to the routing to the...
Altera_Forum's avatar
Altera_Forum
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12 years ago

I think your solution is fine and you didn't have to use the primitives if you didn't want to (see post 2 of this thread: http://www.alteraforum.com/forum/showthread.php?t=20609)

For additional information, you probably want to read the "Gated Clock" section of the recommended coding guidelines: http://www.altera.com/literature/hb/qts/qts_qii51006.pdf (page 12-10).

You may also want to read the Clock Network chapter of the handbook for your device: http://www.altera.com/literature/hb/stratix-iv/stx4_siv51005.pdf (from there you can understand why you can't cascade the ALTCLKCTRL)