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Altera_Forum's avatar
Altera_Forum
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12 years ago

Quartus II clock gating methodology

Hi All

i'm using my FPGA (Stratix IV GX dev kit4) for ASIC prototyping.

we use clock gating all around or design and when i'm using quartus i get poor QOR due to the routing to the clock gater + i can't cascade the clock gaters (based on altera MF ALTCLKCTRL).

i have tried to solve this problem by writing down clock gater ( latch + and gate) by designing them from altera standard cells :

module db_altclkctrl0 (

ena,

inclk,

outclk);

input ena;

input inclk;

output outclk;

wire clk_en_int;

latch latch_i0(ena, ~inclk, clk_en_int);

and and_i0(outclk, clk_en_int, inclk);

endmodule // altclkctrl0

i have tried it and got excellent QOR and i could use the clock gating in cascade.

Does anyone see any issue by using this mode??

Best Regards

Meir

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I think your solution is fine and you didn't have to use the primitives if you didn't want to (see post 2 of this thread: http://www.alteraforum.com/forum/showthread.php?t=20609)

    For additional information, you probably want to read the "Gated Clock" section of the recommended coding guidelines: http://www.altera.com/literature/hb/qts/qts_qii51006.pdf (page 12-10).

    You may also want to read the Clock Network chapter of the handbook for your device: http://www.altera.com/literature/hb/stratix-iv/stx4_siv51005.pdf (from there you can understand why you can't cascade the ALTCLKCTRL)
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Well, it seems to work for you, so take the following with a grain of salt.

    On FPGAs, any kind of logic generated clock tends to have skew issues.

    The two possible approaches to clock gating are (in Altera terms):

    a) use the ALTCLKCTRL that sits atop the clock distribution trees

    b) use the clock gating logic in each LAB.

    For a), you need to use the ALTCLKCTRL functions.

    For b) you should simply code with a clock enable style. 

    always @ (posedge clk)
begin
if(enable) begin
...
end
end

    Alternatively, if you have previously written code which is already gated, you can activate the "Auto-Gated clock conversion" option in Quartus to have the synthesis convert logic gated clocks to "clock enables". Your clock gating modules do need to comply with Quartus' template.

    The clock gating module you posted is not recognized by Quartus and is not converted into a "clock enable". It simply synthesizes to exactly what you've described, which has two bad things for FPGAs: a latch and a logic generated clock.

    The following code does get recognized by the "Auto-Gated clock conversion" option. I do not know if it supports hierarchical clock gating though. 

    module clockGate(
input wire enable,
input wire clkIn,
output wire clkOut
);
reg q;
always @ (negedge clkIn) begin
q <= enable;
end
assign clkOut = q & clkIn;

    References:

    Using Timequest: http://quartushelp.altera.com/current/mergedprojects/logicops/logicops/def_synth_gated_clock_conversion.htm

    Following Altera's clock gating guidelines: http://quartushelp.altera.com/9.1/mergedprojects/verify/da/comp_file_rules_clock.htm

    Lastly, modern synthesis tools for ASIC can generate clock gating from "clock enable" style coding (and a bit more in fact).

    I much prefer to turn that option on and avoid explicit clock gating modules in my RTL code.

    Also, I have this memory in the back of my mind some of the not-so-modern versions have trouble doing STA on designs with multi-stage clock gating.