Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Quartus II Cannot Detect VHDL Signals

Hello,

I'm trying to import my VHDL code as a module to the SOPC; but when I try the new component wizard to analyze my VHDL code, quartus cannot detect any signals and gives: Warning: The component has no signals.

So I cannot import my own design. Furthermore, when I try to generate a system, I keep receiving errors like:

Error: Port clk has type std_logic which is not supported

Error: Port address has type std_logic_vector which is not supported

What may cause the problems? My design works fine on other computers but I could not get it to work in my own. I'm running Quartus II 10.1 sp1 (32 bit) on Win7 64-bit Professional. Thanks in advance.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    i'm new to vhdl myself, but it might be that the types std_logic and std_logic vector are not standard, you could try making those bit and bit_vector and see if that makes a difference,

    either that or you neet to somehow reference the ieee.std_logic_1164.all library. not sure how you'd do that in your over all design or while importing via the wizard
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Make sure you have:

    library ieee;

    use ieee.std_logic_1164.all;

    at the top of your VHDL file.

    Its pretty hard to debug errors in your VHDL code by 'importing' the code into SOPC Builder. First make sure that the code builds with Quartus or Modelsim. That way you won't be confused by VHDL errors, rather than SOPC Builder reported errors.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    i'm new to vhdl myself, but it might be that the types std_logic and std_logic vector are not standard, you could try making those bit and bit_vector and see if that makes a difference,

    either that or you neet to somehow reference the ieee.std_logic_1164.all library. not sure how you'd do that in your over all design or while importing via the wizard

    --- Quote End ---

    std_logic and std_logic_vector are very much a standard, they are just not included in the std.standard library. THey are part of the IEEE VHDL standard. Synthesisors have been using std_logic and std_logic_vector since the dawn of VHDL (and were for a long type the only thing that was supported). They were used because they allowed the description of tri-states that were very common internally to FPGAs at the time. Bit and Bit_vector did not allow tri-stating.