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i'm new to vhdl myself, but it might be that the types std_logic and std_logic vector are not standard, you could try making those bit and bit_vector and see if that makes a difference,
either that or you neet to somehow reference the ieee.std_logic_1164.all library. not sure how you'd do that in your over all design or while importing via the wizard
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std_logic and std_logic_vector are very much a standard, they are just not included in the std.standard library. THey are part of the IEEE VHDL standard. Synthesisors have been using std_logic and std_logic_vector since the dawn of VHDL (and were for a long type the only thing that was supported). They were used because they allowed the description of tri-states that were very common internally to FPGAs at the time. Bit and Bit_vector did not allow tri-stating.
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