Forum Discussion
Altera_Forum
Honored Contributor
14 years agoi'm new to vhdl myself, but it might be that the types std_logic and std_logic vector are not standard, you could try making those bit and bit_vector and see if that makes a difference,
either that or you neet to somehow reference the ieee.std_logic_1164.all library. not sure how you'd do that in your over all design or while importing via the wizard