Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Quartus II beta - WYSIWYG error

Hi I am trying to compile a design in Quarus II 7.2 beta with the following components: - Nios CPU - JTAG - Onchip memory - DDR SDRAM High performance controller - timer I keep ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

The error was not a bug in Quartus II 7.2 beta, but an error in my own design.... I had not noticed that the sdram_clk and the sdram_clk_n are both bidirectional. When this error is fixed the design compiles. I have not tested the design on my board yet, but hopefully everything works....

Regards

Tom