Honored Contributor
Honored ContributorI have gotten that error in both version 7.1 and version 7.1 SP1 copies of a Cyclone III design using the DDR2 SDRAM High Performance Controller. Both times I was editing the design without simultaneously changing the Quartus or DDR2 IP version. If you changed the design at the same time you changed Quartus versions, the error might be from the design change and not a 7.2 beta problem. (I never debugged my error cause. I always tried something else that kept me from having to do anything about the error.)
In case your error was just from upgrading to the beta, I tried recompiling a 7.1 SP1 version of my design using 7.2. I first compiled it without regenerating the DDR2 MegaCore with 7.2; the MegaCore files were the ones from 7.1 SP1. I compiled with no error. I next compiled it after regenerating the MegaCore with 7.2. That also compiled with no error. Of course, my result doesn't rule out a 7.2 beta problem with your design. At least one difference between our designs is that mine does not use SOPC Builder. If you just upgraded the Quartus version without editing anything (or if you can reproduce your error by starting again with a copy of your 7.1 design and just upgrading the version), that probably is supposed to work for your design like it did for mine. I'm not as confident about this, but I expect that you also should be able to recompile a 7.1 design in 7.2 if you regenerated your SOPC Builder system (which probably regenerated the DDR MegaCore). If you know your error isn't from a design change, please file a service request so that Altera can determine whether there is a 7.2 problem with upgrading existing designs without any unintended extra user effort.
