Honored Contributor
Honored ContributorThe guys are pretty spot on here. I find variables can be useful in processes to help sort out intermediate calculations - be damn careful with them as they could synthesise into a register r a wire depending on the order of your code.
As for shared variables: --- Quote Start --- ...but from a C perspective I like local variables more... --- Quote End --- Personally I find it really unhelpful to compare a hardware description language with a software language because they are fundamentally describing different things and are therefore so very different in their nature. Please don't think that this is patronising but remember that you are not writing C; you are describing hardware: gates, registers, counters, adders, multiplexers etc. What lump of logic are you trying to describe with a shared variable? What are you expecting this to synthesise into? If you are starting out with VHDL then, I would say, use signals. You can progress quite happily without using variables at all. Use variables when you understand what they will synthesise into and how the order of your code will affect this. I think it's probably fair to say that for synthesisable code you probably will never have to use variables though. I have only ever used shared variables once - in a high level behavioural bus model to communicate between different procedures in a package. Personally if you are starting out with VHDL I would forget about shared variables - you'll get a very very long way before you need them and when you do, it will be obvious why. I wouldn't be surprised if most VHDL / FPGA designers never feel the need to use shared variables.
