Quartus II 7.2 & Declaring bus range problem

If you are talking of VHDL code for simulation, the behaviour it's very similar to C-programming. The code is interpreted sequentially and you can assign a value to a variable here and there, as long it is anywhere in the namespace.

In synthesizable VHDL, a variable can mean different things. It can be a physical signal, particularly the state of a register. If you define a counter based on a variable, it's just this. Or a variable can be a kind of virtual signal, e. g. a loop variable in an iteration or an intermediate result. It has no physical reality as such and is transformed to something different by the compiler.

As a simple fact, a register can be assigned only one value at a time, also it can have only one valid clock. For this reason, a physical signal can be assigned only in one process or only once in sequential code. Shared variables can't change this facts basically.