Forum Discussion
Altera_Forum
Honored Contributor
17 years agoI've fixed the problem by this:
Setting>Default Parameters> and then redefine MTU and pkt_len_counter I don't know why but it is working. after this I encounter another strange problem: Error (10531): VHDL Variable Declaration error at Ser.vhd(56): variable declared outside subprogram or process must be a shared variable why? I've fix this problem by using shared varibale:
architecture Ser_arch of Ser is
signal label_mem : std_logic_vector((Label_Width-1) downto 0);
signal data_mem : std_logic_vector((MTU-1-32) downto 0);
signal counter_mem : std_logic_vector((Counter_Width-1) downto 0);
signal prtc_flag : std_logic; -- Packet ready to Combine
-- prtc_flag uses as signal and it's just the AND of 4 ports.
variable sr : unsigned((SOF_len+Label_Width+MTU+SOF_len-1) downto 0);
variable cnt : integer;
variable tmp : std_logic_vector((SOF_len+Label_Width+MTU+SOF_len-1) downto 0);
-- =====================function decleration=======================
-- crating function to convert the std_logic_vcetor to integer:
function TO_INTEGER_stdvect (ARG: std_logic_vector) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XXARG: std_logic_vector(ARG_LEFT
......
......
Why this is necessary to define the shared values I just use this variable in current architecture... sth strange...