Quartus II 13 problem! bumping on this one

Hi Anakha, here is the qsf file, thanks for the help:

# --------------------------------------------------------------------------#

#

# Copyright (C) 1991-2013 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors. Please refer to the

# applicable agreement for further details.

#

# --------------------------------------------------------------------------#

#

# Quartus II 64-Bit

# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition

# Date created = 10:48:14 December 13, 2013

#

# --------------------------------------------------------------------------#

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

# VHDL_uppgift_4ny_assignment_defaults.qdf

# If this file doesn't exist, see file:

# assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

# file is updated automatically by the Quartus II software

# and any changes you make may be lost or overwritten.

#

# --------------------------------------------------------------------------#

set_global_assignment -name FAMILY "Cyclone IV E"

set_global_assignment -name DEVICE EP4CE115F29C7

set_global_assignment -name TOP_LEVEL_ENTITY VHDL_uppgift_4ny

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:48:13 DECEMBER 13, 2013"

set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

set_global_assignment -name VHDL_FILE VHDL_uppgift_4ny.vhd

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"

set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id eda_simulation

set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4ny_vhd_tst " -section_id eda_simulation

set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4ny_vhd_tst " -section_id eda_simulation

set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id "VHDL_uppgift_4ny_vhd_tst "

set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ms" -section_id "VHDL_uppgift_4ny_vhd_tst "

set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME "VHDL_uppgift_4ny_vhd_tst " -section_id "VHDL_uppgift_4ny_vhd_tst "

set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/VHDL_uppgift_4ny.vht -section_id "VHDL_uppgift_4ny_vhd_tst "

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top