Quartus II ロジック・エレメント 0 教えて

Thank you for your reply.

I attached the project file.

For the time being, the program only confirmed that there were no compilation errors.

The Quartus 2 I am using is ver14.1.

Same question closed. please check.

Thanks.

Machida

Thank you for your email on 09/09/2022.
I really want to solve it, so please help me.

Thanks.
Machida

Hi,

Thank you for attaching the files.

No worries, I'll compile the project and please give me some time to investigate on the problem you faced.

Thanks.

Best Regards,

Ven Ting

Hi,

1. The logic utilization is displaying N/A and the total registers is 0.

This is because DFF_inst9, DFF_inst4, and DFF inst7 are removed during Analysis & Synthesis stage. The reasons for the removal of these registers is as shown in ss_Register Statistics.jpg.

2.To solve this, you need to change the circuitry connection. Make sure the clock port of the DFF is fed to a clock.

For instance,

DFF_inst9, stuck at gnd due to stuck port clock

From the RTL viewer, the clock port of DFF_inst9 is constantly fed to 1’h1 not to a clock. It should be connected to a clock. Since the clock signal is constant, the output of DFF_inst9 will also be a constant. Thus, when the synthesis tool performs certain optimizations, it will reduce the logic and cause the DFF to optimize away.

DFF_inst7, stuck at gnd due to stuck port data_in

Since the data input port (D) is fed to the output of DFF_inst9 which is a constant value, so the DFF_inst7 is also optimized away.

DFF_inst4, stuck at gnd due to stuck port data_in

The data input port of DFF_inst4 is fed to ground. Thus, the synthesis tool will optimize the DFF away.

Besides, the removal of registers (DFF_inst9, DFF_inst7, and DFF_inst4) have led to the removal of other registers as well as shown in ss_Register Statistics.jpg. You may find the reasons in the report in Quartus. Go to the Compilation Report > Analysis & Synthesis > Optimization Results > Register Statistics.

To sum up, when you have a constant signal that gets stuck at ground, the synthesis tool will perform logic optimization and optimize away your design. This affects other registers connected to it and causes the register to be removed as well. As a result, you can get 0% logic utilization.

You may check out the links below:

Netlist Viewer User Interface

https://www.intel.com/content/www/us/en/docs/programmable/683230/18-1/netlist-viewer-user-interface.html

Related forum on analysis and optimization

https://community.intel.com/t5/Programmable-Devices/analysis-and-optimization-problem/td-p/183323

Please let me know if the explanations above answer your questions.

Thanks.

Best Regards,

Ven Ting

Hi,

May I know any updates from you? Are the explanations above helpful?

Thanks.

Best Regards,

Ven Ting

Hi,

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Ven Ting

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.