library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity c74163_0_5 is
port(
     LDN    : in std_logic;
     CLRN   : in std_logic;
     CLK    : in std_logic;
     RCO    : out std_logic
);
end c74163_0_5;

architecture b74163 of c74163_0_5 is
	signal Qint: std_logic_vector(4 downto 0);
	signal ENP:std_logic;

--		***************************************
--		Set delay by no of pulses to A,B,C,D,E.  
--		***************************************	
--		Setable data to Qint:
--					11111(min. delay) to 00010(max.)
--						Order;E  D  C  B  A  
--					if(LDN = '0')then Qint <="EDCBA";
begin

ENP <= '1';

	process (CLK, CLRN)begin

		if(CLRN = '0')then  Qint <= "00000"; 	
		
			elsif( CLK'event and CLK='1' )then 
-- *****No. of delaied pulses is set to Qint***********			
			if(LDN = '0')then Qint <="10101";
			
			elsif(ENP='1') then Qint <= Qint + 1;
			
		   end if;
			
		end if;
		
	end process;

 RCO  <=Qint(4) and Qint(3) and Qint(2) and Qint(1) and Qint(0) and ENP;

end b74163;