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APack
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7 years ago

Quartus ignoring delay/skew constraints but not giving a warning

Hi, I am using Quartus 15.0.2 (just before prime came in) and a cyclone 5CGX. I am trying to do clock reconstruction using a data and strobe line (both pins into the FPGA) this obviously requires a...
APack's avatar
APack
Icon for New Contributor rankNew Contributor
7 years ago

Does the comma not delineate the 2 ports I'm trying to constrain? I tried removing it and rebuilding and once again has had no effect, I tried in timequest and got no errors for either syntax but when building using them in the .sdc file they appear to take no effect and there is no mention of them in the console