Quartus Global Reset assignment

I am working on Quartus V13.0 sp1 on incremental compilation mode,

and use partition by bottom up way.

Sub modules are compiled in separate project then export / import to the top module.

My custom modules are interfaced to Qsys, and this problem is happening in custom modules only.

I can assign some global clock to same CLKCTRL_Gx in top module and sub modules.

But I can not assign global reset signals in same way.

It works in any sub modules, but when I merge all sub module to top module,

global reset signal name is changed automatically.

Please tell me how to fix CLKCTRL_Gx number for the reset signals.

Also I wonder if top module CLKCTRL_Gx and sub module CLKCTRL_Gy is different,

Are those clocks still physicaly connected together ?

//................ top module ................................................

set_global_assignment -name AUTO_GLOBAL_CLOCK OFF -tag BOTTOM_UP_SCRIPT_AUTO_GENERATED

set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS OFF -tag BOTTOM_UP_SCRIPT_AUTO_GENERATED

set_instance_assignment -name GLOBAL_SIGNAL_CLKCTRL_LOCATION CLKCTRL_G9 -to reset_cold_250M_

set_location_assignment CLKCTRL_G29 -to "altpll_ckio:......_pll1_clk[0]~clkctrl"

//............................................................................

create_clock -name {ckio_in} -period 10.000 [get_ports {ckio_in}]

create_clock -name {reset_fpga_} -period 10.000 [get_ports {reset_fpga_}]

create_generated_clock -name {ckio_250M} -source [get_pins {pll_ckio_....|inclk[0]}]

-multiply_by 5 -divide_by 2 -master_clock {ckio_in} [get_pins {pll_ckio_a|.....|pll1|clk[0]}]

create_clock -name {reset_cold_250M_} -period 4.000 [get_registers {reset_cold_250M_}]

//............................................................................

input reset_fpga_, ckio_in;

wire ckio_250M, ckio_125M, PLL1_locked;

reg reset_cold_250M_, reset_cold_250M_t;

altpll_ckio pll_ckio_a (.inclk0(ckio_in), .c0(ckio_250M), .c1(ckio_125M),

.areset(~reset_fpga_), .locked(PLL1_locked));

always @(posedge ckio_250M or negedge reset_fpga_) begin

if (~reset_fpga_) begin

reset_cold_250M_t <= 1'b0;

reset_cold_250M_ <= 1'b0;

end

else if (PLL1_locked) begin

reset_cold_250M_t <= 1'b1;

reset_cold_250M_ <= reset_cold_250M_t;

end

end

//................ sub module ................................................

set_global_assignment -name AUTO_GLOBAL_CLOCK OFF -tag BOTTOM_UP_SCRIPT_AUTO_GENERATED

set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS OFF -tag BOTTOM_UP_SCRIPT_AUTO_GENERATED

set_instance_assignment -name GLOBAL_SIGNAL_CLKCTRL_LOCATION CLKCTRL_G9 -to reset_cold_250M_

set_instance_assignment -name VIRTUAL_PIN ON -to reset_cold_250M_

//............................................................................

create_clock -name {reset_cold_250M_} -period 4.000 [get_ports {reset_cold_250M_}]

//............................................................................

input reset_cold_250M_; // sub module

//............................................................................