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Note that I recommend against using this assignment. If you use timing constraints to constrain your design, the fitter will use I/O registers when need be.
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Interesting, can you elaborate a bit more. I realize the trade-off with internal timing, but I use to force fast I/O, at least in two cases.
One is when using fast async devices, such as ASYNC SRAM. That was a PITA to constraint, at least until recently. I understand that Quartus 9 supports data skew constraints that might help here, but I didn't try that yet.
The second case is when using a PLL phase shift, such as with SDRAM. You need to know the internal delays before computing the ideal phase shift. And you can't reliably do that without fast I/O. I agree that if you constraint and meet timing, then in theory you are ok, even when the fitter decided to not use fast I/O. But this might mean the phase shift is not optimized, giving you a smaller I/O timing slack.
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