Quartus Fitter messages

If your constraints are correct, then static timing analysis will tell you if you made timing, and whether an I/O register is used is irrelevant. It can take getting used to, but I see this method on most designs.

(As an aside, there was an architecture put out many, many years ago that didn't have an I/O register, but had a really fast connection between the LAB registers and the I/O. From a timing perspective there really wasn't much difference, but a number of people were very unhappy, whether it met their requirements or not...)