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jch4416's avatar
jch4416
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Quartus fitter ignores the RTL generated by the synthesis

Hello,

I am getting started with a simple Verilog project for a CPLD. The first thing I have to implement is a clock divider for the 50MHz clock on my eval board. My code works when I place it directly in the top level module. The design uses 30 of the available 240 LEs. However when I place the same code in a separate module and instantiate the clock divider module, the fitter reports using 0 LEs and the code does nothing. But in the RTL Viewer, I can see the clock divider module and the synthesis report says it used 30 LEs.

It doesn't matter if I put the clock divider module in a separate file or in the top level file.

Has anyone seen this type of thing before?

Thanks,

Jim

  • jch4416's avatar
    jch4416
    5 years ago

    I found the issue that was causing the fitter to ignore all the RTL, but I could use some help understanding it.

    In the top module, I defined a reg variable called reset_n that I wanted to use as a master power on reset. Then I had an initial block in the top module to assert and de-assert the reset_n.

    initial
    begin
    reset_n <= `LO;
    #10 reset_n <= `HI;
    end

    This worked fine when I put the clock_divider() code directly into the top module.

    But when I tried to instantiate clock divider modules, I put reset_n into their port lists and the fitter gave me a message like "reset_n has no source, setting to GND". With reset_n always asserted, the clock_divider produced no clock output so it was apparently optimized out.

    Any ideas why this happened? Can I not define an internal power on reset? Perhaps I don't need to? I had the "POWER UP DON'T CARE" setting OFF. I had read this causes all registers to initialize to 0

13 Replies

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi Jim,


    By default, it should be working if you place direct or separate module. May I know what type and version of Quartus you are using? Can you attach the design files for both place module directly and separately. I will try to duplicate it.


    Thanks,

    Regards


    • jch4416's avatar
      jch4416
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Thanks for your help Syafieq. I have attached 2 zip files. Both contain the .qsf and .qfp files. the

      The Proj_separate_modules archive has 2 Verilog files, one for the top level module and one for the clock divider. the top level instantiates the clock divider. This project compiles without errors and the synthesis produces RTL which uses 34 logic elements. But the fitter doesn't place anything on the chip.

      The Proj_one_module archive pastes the code from the clock divider module directly into the body of the top module. And produces a working programmable for the cpld with 34 LEs fitted.

      The variable master_8mhz_clk is actually being used for a 50MHz clock on my eval board. The target hardware will use 8MHz.

      Jim

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        5 years ago

        Your instantiation is incorrect. You're missing an instance name. And while it's not part of the issue, best practice is to do a full port mapping. So it should look like this:

        clock_divider u1 (.clk_in(master_8mhz_clk), .reset_n(reset_n), .clk_out(test_led));

    • jch4416's avatar
      jch4416
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi Syafieq,

      I am using the Quartus Prime Lite edition, v20.1.0 Build711.

      Thanks for your help,

      Jim

      • jch4416's avatar
        jch4416
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        I found the issue that was causing the fitter to ignore all the RTL, but I could use some help understanding it.

        In the top module, I defined a reg variable called reset_n that I wanted to use as a master power on reset. Then I had an initial block in the top module to assert and de-assert the reset_n.

        initial
        begin
        reset_n <= `LO;
        #10 reset_n <= `HI;
        end

        This worked fine when I put the clock_divider() code directly into the top module.

        But when I tried to instantiate clock divider modules, I put reset_n into their port lists and the fitter gave me a message like "reset_n has no source, setting to GND". With reset_n always asserted, the clock_divider produced no clock output so it was apparently optimized out.

        Any ideas why this happened? Can I not define an internal power on reset? Perhaps I don't need to? I had the "POWER UP DON'T CARE" setting OFF. I had read this causes all registers to initialize to 0