Quartus fitter ignores the RTL generated by the synthesis

Hello, take care this is a VHDL oriented and is long time is no more using a CPLD.

Your design has no external reset pin and delay is just useful for simulation not synthesis.

Again your module is sensing at same time both negative edge of Reset_n and positive of clock, this is a non synthesis reason. This require dual edge flip flop not present on CPLD nor FPGA.7

CPLD FF can be reset in async way, FPGA one prefer to be synced to main clock. Move reset forward as level under clock control.

CPLD's carry limited resources and using sync reset if not natively supported consume 2 FF instead of one. This case require controlling reset by level not edge. Move as level in front of clock control.

Using delay get sentence to be optimized out most of time from synthesis.

MaxII MaxV perform internal POR reset, but no idea how to instantiate or if useable on design.

About similar issue yes but your is due to error in design.

Mine got from intermixing VHDL and Verilog module, sometimes port signals of correctly designed (working too) where randomly corrupted but on complex design and QSYS control. This the reason I analysed your design, nothing to do what I seen my side.

forgot answer this:

>> Any ideas why this happened? Can I not define an internal power on reset? Perhaps I don't need to? I had the "POWER UP DON'T CARE" setting OFF. I had read this causes all registers to initialize to 0

Yes it initialize to 0 at Power up and never after. Preload is done one time, reset has to be added in some way.

Your design appear as more MCU centric than CPLD, maybe you converted some software from C language to (System)Verilog. Warning, it resemble C but is it NOT! Verilog is an HDL language, sentences get executed in parallel not sequentially.

To save you time, MAX V similar part is cheap, take care about pin assignment: is close but not same.