quartus error

on cyclon IV E EP4CE115F29C7

i have a ddr controller module connected to altera internal ram. during compilation i get this:

Error: Memory block iliamemory:inst4|altsyncram:altsyncram_component|altsyncram_joj2:auto_generated|ram_block1a15 uses a global signal on its clock-enable1 port. This is not allowed for this family.

it just drives me nuts! my memory megafunction does not contain any clock-enable port. i just have a clock generated from pll and that clock goes into DDR controller aswell as in my altera RAM. when i double click the error it takes me here:

ram_block1a15 : cycloneive_ram_block

WITH (

CLK0_CORE_CLOCK_ENABLE = "none",

CLK0_INPUT_CLOCK_ENABLE = "none",

CONNECTIVITY_CHECKING = "OFF",

LOGICAL_RAM_NAME = "ALTSYNCRAM",

MIXED_PORT_FEED_THROUGH_MODE = "dont_care",

OPERATION_MODE = "bidir_dual_port",

PORT_A_ADDRESS_WIDTH = 9,

PORT_A_DATA_OUT_CLEAR = "none",

PORT_A_DATA_WIDTH = 1,

PORT_A_FIRST_ADDRESS = 0,

PORT_A_FIRST_BIT_NUMBER = 15,

PORT_A_LAST_ADDRESS = 511,

PORT_A_LOGICAL_RAM_DEPTH = 512,

PORT_A_LOGICAL_RAM_WIDTH = 32,

PORT_A_READ_DURING_WRITE_MODE = "new_data_with_nbe_read",

PORT_B_ADDRESS_CLOCK = "clock0",

PORT_B_ADDRESS_WIDTH = 9,

PORT_B_DATA_IN_CLOCK = "clock0",

PORT_B_DATA_OUT_CLEAR = "none",

PORT_B_DATA_WIDTH = 1,

PORT_B_FIRST_ADDRESS = 0,

PORT_B_FIRST_BIT_NUMBER = 15,

PORT_B_LAST_ADDRESS = 511,

PORT_B_LOGICAL_RAM_DEPTH = 512,

PORT_B_LOGICAL_RAM_WIDTH = 32,

PORT_B_READ_DURING_WRITE_MODE = "new_data_with_nbe_read",

PORT_B_READ_ENABLE_CLOCK = "clock0",

PORT_B_WRITE_ENABLE_CLOCK = "clock0",

POWER_UP_UNINITIALIZED = "false",

RAM_BLOCK_TYPE = "M9K"

);

one strange thing.. if i delete pll generated clock on the ddr controller. and connect it to a input port, then it compiles with no errors. what can i do? tried everything... 3 days iv been wrestling with this misterious error.