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ZAhma1's avatar
ZAhma1
Icon for New Contributor rankNew Contributor
7 years ago

Quartus error 13223 during synthesis on IP file generated by Quartus

I am porting a design from Quartus 16.1 to Quartus 19.2. I've followed the user guide and have cleared most warnings and errors and upgraded IP files. One of the IPs generated by Quartus fails to l...
JoanneSinY_L_Intel's avatar
JoanneSinY_L_Intel
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
​Hi I am using same quartus version as your. Is this possible to share me the design .qar file Btw, do you able to open those Verilog file using file tab in quartus? Can you remove those Verilog file in the error and add again Thanks Joanne