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ZAhma1's avatar
ZAhma1
Icon for New Contributor rankNew Contributor
6 years ago

Quartus error 13223 during synthesis on IP file generated by Quartus

I am porting a design from Quartus 16.1 to Quartus 19.2. I've followed the user guide and have cleared most warnings and errors and upgraded IP files. One of the IPs generated by Quartus fails to l...
ZAhma1's avatar
ZAhma1
Icon for New Contributor rankNew Contributor
6 years ago

Hi Joanne,

I tried using a manual set_global_assignment as you said, but it did not work.

I then tried to create a new empty project with the same device, and only add the ip file for the failing block. I see the same issue here too. I've attached the project to this message. Please take a look and let me know.

Thanks!

--Zohair

JoanneSinY_L_Intel's avatar
JoanneSinY_L_Intel
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

​Hi Zahma,

I am able to run the compilation using quartus version 19.1 without getting the error above.

When I run the design using quartus 19.2, I am not able to replicate the error as you mention. But I get the ' Error(16368): Top-level design entity "test_191" is undefined '

So, I change the setting in the .qsf file and generate HDL of the IP using platform designer

set_global_assignment -name TOP_LEVEL_ENTITY fft_ii_2048

May I know is this your top level file?

Attached is the design file

Thanks

Joanne