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Altera_Forum
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18 years ago

Quartus Error - Simulated vs Expected Result

Hello all, I am a newbie to Quartus and VHDL. I am getting an error when trying to simulate a VHDL code. It compiles successfully though. The error is "Simulation results do not match ex...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi,

There is a check box in the simulation settings that makes the simulator check the VWF file with the simulation result, to see if there is any difference. This can be really handy if you know the resulting waveforms you are after. You dont need to go through and check it, the tool will just tell you.