Forum Discussion
Altera_Forum
Honored Contributor
16 years agoUnfortunately the design is to large to be posted here (over 51K characters). If you want I can send you an e-mail with the design attached, or you can generate it by the downloading an SVN version of the FloPoCo project:
svn checkout svn://scm.gforge.inria.fr/svn/flopocoand writing the command: #./flopoco -frequency=200 FPLog 8 23 7The design is generated from FloPoCo arithmetic core generator and represents a floating point logarithm on simple precision FP numbers. The target frequency is 200MHz on Virtex4, I want to optimize it for StratixII to run at the same frequency and use fewer logic resources than the default implementation. The first step would be to substitute the rom_extract attribute in the architecture of the IntIntKCM_8_93032640 component by something that quartus recognizes. That would place KCMFirstTable_6_33 component into ROM memory. Thx a lot for helping, I really appreciate it. Benny