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a DSP chip is processor designed for digitial signal processing. You can get ones that work in fixed or floating point:
https://en.wikipedia.org/wiki/digital_signal_processor If you try and make 57600 PEs in a single FPGA, you're doomed to failure. For a start, your image (240x240) will not arrive in parrallel. You will get the data as a streaming set of pixels. Then you need to calculate the results in series.
Also, the algorithm looks about ready for some re-design, and I dont understand why it cannot be fixed point. If you know the width of the inputs, then you can with out the max width of U.
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Tricky, thanks as always for your support. 57600 PE might be an exaggeration (I could actually implement only 1.000 pixels for sake of simplicity) , but the way data get PE is actually not relevant (according to the specs of my project), Once each data is in "position" is when the processing must start. In the other hand. I'm thinking to reformulate my project to use my board DE1-SOC's resources. Do you think I could use NIOS-II and C or Assembly programming language for the equation above for (let's say) 1.000 independent and parallel cores (in a way which makes sense)?
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