Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Quartus complaint: My LOOP is too big? But the code is from the book, what's wrong?

Hello friends. I'm trying to make addition and subtraction of floating point. My guide is a book "Computer Arithmetic and Verilog HDL Fundamentals" by Cavanagh. Inside the module he use a code for al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

a DSP chip is processor designed for digitial signal processing. You can get ones that work in fixed or floating point: https://en.wikipedia.org/wiki/digital_signal_processor

If you try and make 57600 PEs in a single FPGA, you're doomed to failure. For a start, your image (240x240) will not arrive in parrallel. You will get the data as a streaming set of pixels. Then you need to calculate the results in series.

Also, the algorithm looks about ready for some re-design, and I dont understand why it cannot be fixed point. If you know the width of the inputs, then you can with out the max width of U.