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In that case - stick with the altera floating point IP cores rather than trying to write your own floating point arithmatic.
This is of course, if there is no chance you can redesign the algorhith to fit with an FPGA. If you want lots of floating point (and especially division - which is particularly expensive in FPGA) why not use a DSP?
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Tricky, sorry for the question, this DSP you mentioned is like an accessory chip in the development board, or is it the NIOS-II?
In theory. I would need about 57.600 Processing Elements (240 x 240 pixels from a black and white picture) , Each processing element calculates an equation like this
http://www.alteraforum.com/forum/attachment.php?attachmentid=11768&stc=1 where A = is a positive integer from 0 to 255, 1 pixel = 1 processing element, (B, X and Y start with random numbers which will update by addition of the others pixels-PE results, but that's a different story) which I expected to implement in hardware somehow.
In fact, since this is a school project, requirements are pretty flexible, so I have the freedom to use any technology (But I have later to explain the reason).
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