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The code from the book looks like it was written for use in a simulator. This code clearly cannot be synthesized.
Are you are studying how to develop hardware for doing floating point? Unless that is the case, using floating point in an FPGA is not the best solution. If your goal is to do a parallel calculation, you should convert your problem domain to integer or fixed point. Nearly every computation using physical world data can be done with integers or fixed point. Study numerical methods to see how this is done. Once you've converted your problem space then you can start your FPGA work.
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I'm not sure what parallel calculation means, but isn't exactly what the above code is trying to do? It is, to separate exponents and fractions and consider them Integers, doing subsequent separated evaluations. Yet, it needs of this awkward loops. If is not, what is this numerical method which I should search for?
Now, I understand if I follow the book's method, Quartus will end generating at least 255 (If I manage to set configuration files) hardware units, which may or may not be used depending of the value reached by "ctrl_align", I wonder, is this completly wrong to do if my goal is not only to simulate but to actually fabricate a chip?
I will briefly explain what I'm trying to do, you may remember something of my previous posts.
I want to design a chip, this chip performs the calculation of an equation known as "FCM" (Fuzzy C means). Equation itself includes iterative additions, subtraction, multiplication and division. Because it performs iterative divisions, fractional numbers are necessary, otherwise It will end giving me a wrong results. From my point of view, I should create a logic in Verilog able to do this, using Quartus and Synthesis simulation of what should become in a chip later. So, is this the way to do it, or am I wrong?
I've searched in internet, there is a lot of material regarding Floating Point operations in verilog, they say efficient, but efficient enough for a real chip? Idk
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