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You realise there is a big difference between HDL and procedural languages right?
Loops make little sense in hardware - it doesn't run as a loop, the synthesizer breaks it all up into hardware - so if you did a loop that added 1 four times, it would probably make a chain of four adders each adding 1.
In your case, how does the synthesizer know when to stop? If ctrl_align was say 10, it would require 10 copies of the hardware. If it was 20, it would require 20 copies of the hardware. So how does it know how many to put?
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Yes sir, I have been reading more information and I understand what you say. Although, I'd like to point that this code is from book itself. I'm learning Verilog just recently, and Bibliography is very confusing and contradictory for a beginner. I was trying to make Floating Point operation, and Cavanagh book take this behavioral path. So I wonder, if is senseless to make such of operations by this way, why to write a whole book under this concept, while it should really be implemented differently? This is not a general book, it is about arithmetic in verilog. My first impression was that, it would be ok to use this model, and there is not a better way.
What way do you personally would suggest, considering this is a hypothetical real life implementation?
One more thing, it seems that is possible to Set .qsf files to a different number, Quartus complaint that 250 is the highest set, and my ctrl_aligh is 8 bits, that would be 255, so I just need to change that setting in the files?
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