Honored Contributor
Honored ContributorTa for the reply... but not really what I'm after... for example the default Synthesis report from Webpack for a simple serial ADC FSM / Shiftregister implementation gives:
========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit <pxf_adc>. Related source file is "R:/projects/asl0600/Users/dc/Bladerunner/Source/Pxf/new/pxf/PxfAdc.vhd". Found finite state machine <FSM_0> for signal <adc_state>. ----------------------------------------------------------------------- | States | 7 | | Transitions | 12 | | Inputs | 4 | | Outputs | 5 | | Clock | clk (falling_edge) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset State | adc_state_idle | | Power Up State | adc_state_idle | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <aconv>. Found 14-bit register for signal <adc_data_hold>. Found 1-bit register for signal <adc_conv_done>. Found 14-bit register for signal <adc_data>. Found 1-bit register for signal <asdo_reg>. Found 6-bit up counter for signal <clk_count>. Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 31 D-type flip-flop(s). Unit <pxf_adc> synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Analyzing FSM <FSM_0> for best encoding. Optimizing FSM <FSM_0> on signal <adc_state[1:3]> with sequential encoding. --------------------------------- State | Encoding --------------------------------- adc_state_idle | 000 adc_state_wait_ch0 | 001 adc_state_shift_ch0 | 010 adc_state_latch_ch0 | 011 adc_state_wait_ch1 | 100 adc_state_shift_ch1 | 101 adc_state_latch_ch1 | 110 --------------------------------- Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Counters : 1 6-bit up counter : 1 # Registers : 21 1-bit register : 20 14-bit register : 1 Which tells me everything I need to know about how the tools are turning my VHDL into real logic at the high level... I'm not really that worried about what it generates at the gate level... Is there a way to get the same sort of info out of Quartus? At present during compilation all Quartus tells me is that it found 1 entity and 1 architecture in the file... and after synthesis how many cells of what type it is using (Analysis & Synthesis Resource Utilization by Entity report)... but with no indication of how its using them... How do I know that 6 of the LC register are a 6-bit up counter or that another 14 are making up the shift-register? Brad, you also said "The Analysis & Synthesis report also give details about every state machine in messages and in tables"... I must be dumb, but I can't appear to find any info about the FSMs and how it is auto-encoding the states ;) ... What tab in the report is this on? Thanks, Dave
