Quartus Compilation Report

The number of pins you have is indeed massive. May be you have plenty of buses in some of your modules and the fitter was left free to assign them to pins(you may have an intermediary module set as top level instead of final project top).

i only have top module which have 4x4 inputs of each is std_logic_vector(15 downto 0) same goes to the outputs. Is that the reason that contributes to the massive amount of pins?

4 x 4 x 16 = 256 inputs

ya, you are rite! thanks!

Your pins are inherent to your design ??? Any change -usually -requires a respin of the entire board. Anyway look at what you want and may be can do with less pins.

if i need to perform image processing, what is the appropriate way to handle the inputs and outputs without exceeding the device resource?

Can't you byte-interface external to fpga then process inside fpga at higher suitable speed?

I don't know about your setup but usually in 2-D image processing engineers wouldn't flood the board with so many pins and connections equal to the number of a frame. A frame is processed inside the fpga at whatever suitable speed.

so in that case i need to use some memory to hold the input and output then?